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i 2 c bus-compatible audio/video switch with electronic volume description the CXA2078Q is an i 2 c programmable audio, video switch designed for set top box applications. it interfaces from digital encoder sources to tv, vcr and auxilliary scart connectors. features 3 scart independent audio/video switching (tv, vcr, aux) 0 to ?3db volume control with click noise reduction 5 stereo audio inputs i 2 c control with two address setting scart function switching input and output scart fast blanking for osd rf modulator output with y/c mix option on-chip +12v to +9v voltage regulator 4 logic outputs applications audio/video switch featuring i 2 c bus compatibility for set top box structure bipolar silicon monolithic ic absolute maximum ratings supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 500 mw operating conditions supply voltage +10.7 to +12 v operating voltage 9 0.5 v ?1 e97843-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA2078Q 64 pin qfp (plastic)
?2 CXA2078Q pin configuration 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 vout2 fblk_out vout1 v cc _12v vreg_9v vreg_base video_v cc rin5 fblk_in2 lin5 vin1 rin1 vin3 rout1 vout5 lout1 vout6 rout2 vout7 lout2 audio_v cc vin12 bias_audio vin8 lin3 vin4 rtv vout3 ltv vout4 dig_v cc log_1 log_2 log_3 log_4 dig_gnd fblk_in1 hw mute lin4 fnc_tva fnc_tvb rin4 trap mono vout8 lin1 vin5 bias_video vin9 fnc_vcr vin6 fnc_aux vin10 video_gnd scl sda adr audio_gnd vin7 rin2 vin11 lin2 vin2 rin3
?3 CXA2078Q bias 2 4.5v bias 1 2 3 5 7 9 10 11 12 13 20 23 25 40 42 43 44 45 46 47 55 56 57 58 64 5v 0v comparator comparator 2 2 fblk_sw video switch1 (tv) 2 2 video switch2 (vcr) 2 2 video switch3 (aux) 2 8db step 1db step att. att. att. att. att. 2 8db step 1db step att. att. att. att. att. audio switch2 (vcr) z.c.d logic 2 2 audio switch3 (aux) 2 2 6k 6k 6k 6k 6k 6k 6k 6k 6k 6k audio switch1 (tv) volume control & mute bias mute 4.5v bias 2 17 21 39 61 1 15 19 36 59 63 2 4 6 8 14 16 22 24 18 41 60 62 fblk_in1 fblk_in2 vin1 vin2 vin3 vin4 vin5 vin6 vin7 vin8 vin9 vin10 vin11 vin12 rin1 rin2 rin3 rin4 rin5 lin1 lin2 lin3 lin4 lin5 26 27 28 29 30 38 37 35 34 31 32 33 48 49 50 51 52 53 54 fblk_out vout1 (blue) vout2 (green) vout3 (red/chroma) vout4 (cvbs/luma) vout5 (chroma) vout6 (cvbs/luma) vout7 (cvbs) vout8 (cvbs) trap rtv ltv 9v reg 4.05v v cc _12v vreg_base vreg_9v video_v cc bias_video video_gnd audio_v cc bias_audio audio_gnd dig_v cc dig_gnd sda scl adr fnc_vcr fnc_aux hw mute logic p.o.d i 2 c interface mono rout1 lout1 rout2 lout2 fnc_tva fnc_tvb log_1 log_2 log_3 log_4 tv aux vcr rf mod tv rf mod aux vcr tv input attenuation = 6db with 6k external resistor. monitor mix_sw y/c mixer typical load typical configuration source output mode1 mode2 aux enc digital (osd) aux digital (osd) aux digital (osd) digital (no osd) vcr aux digital (osd) digital (no osd) vcr aux blue blue green green red red cvbs cvbs cvbs cvbs cvbs chroma chroma luma luma luma luma chroma chroma (osd = on-screen display) mute block diagram
?4 CXA2078Q pin description pin no. symbol pin voltage equivalent circuit description 2 4 6 8 14 16 18 20 22 24 64 62 v cc = 9v v cc = 12v 14a 120k 147 60a vin1 vin2 vin3 vin4 vin5 vin6 vin7 vin8 vin9 vin10 vin11 vin12 4.6v video signal inputs. input impedance typically 120k . 62 18 64 20 2 6 14 22 4 8 16 24 15 17 19 21 39 36 59 63 61 1 v cc = 12v 27k 33k 7a 4.5v rin1 rin2 rin3 rin4 rin5 lin1 lin2 lin3 lin4 lin5 4.5v audio signal inputs. input impedance typically 60k . 63 15 19 36 59 1 17 21 39 61 27 29 31 33 48 50 52 54 v cc = 12v 200 280a 140f v cc = 9v vout1 vout2 vout3 vout4 vout5 vout6 vout7 vout8 3.9v video signal outputs. 54 52 50 48 31 29 27 33 26 28 30 32 49 51 v cc = 12v v cc = 9v 33a 20k 33a 22k 20k 55 rtv rout1 rout2 ltv lout1 lout2 4.5v audio signal outputs. 51 32 28 49 30 26
?5 CXA2078Q pin no. symbol pin voltage equivalent circuit description 34 v cc = 12v v cc = 9v 75a 20k 200 200 75a mono 4.5v audio mono signal output. 34 3 v cc = 12v v cc = 9v 14a 200 11k 9k bias_ video 3.9v reference bias for video circuit. connected to gnd with capacitor. 3 v cc = 12v v cc = 9v 20k 20k 7a 23 bias_ audio 4.5v reference bias for audio circuit. connected to gnd with capacitor. 23 38 37 v cc = 12v 2.7v v cc = 9v 20k 40k fnc_tvb fnc_tva i 2 c controlled output giving 0/2v. maximum load current = 800? 37 38
?6 CXA2078Q pin no. symbol pin voltage equivalent circuit description v cc = 12v 77.7k 13.5k 120a 56 vreg_9v 9v pin connected to emitter of external regulator transistor. 56 v cc = 12v v cc = 12v 120a 57 413 1ma 15p vreg_ base 9.7v connection to base of external regulator transistor. 57 40k 10k 4k 10 v cc = 9v 40a scl i 2 c clock input. v il = 1.5v (max) v ih = 3.0v (min) 10 40k 4.5k 4k v cc = 9v 40a 11 sda i 2 c data input/output. v il = 1.5v (max) v ih = 3.0v (min) v ol = 0.4v (max) 11
?7 CXA2078Q pin no. symbol pin voltage equivalent circuit description 40 28k 72k v cc = 12v 147 12 adr hw mute hw mute: this pin is active high > 2.5v. when high, audio outputs rtv, ltv and mono are muted. adr: selects the i 2 c address for the ic. < 1.5v = low add = 90h > 2.5v = high add = 92h 12 40 43 44 45 46 v cc = 12v v cc = 9v 4.5k 7.5k 40k 3v 8a log_4 log_3 log_2 log_1 open collector logic pins. maximum current sink = 1ma 43 44 45 46 v cc = 12v v cc = 9v 470a 1k 147 35 trap 3.9v connection to external trap circuit. trap components should be kept as close as possible to this pin. 35 v cc = 9v 53 v cc = 12v 100a 100a 100 fblk_ out fast blank output set by i 2 c, fblk_in1 or fblk_in2. high = 5.1v low = 1.2v connected to external emitter follower. maximum load current = 800? 53
?8 CXA2078Q pin no. symbol pin voltage equivalent circuit description 60 90a 50a v cc = 12v 147 41 v cc = 9v fblk_in1 fblk_in2 fast blank inputs. low = < 0.4v high = > 1.0, < 3.0 41 60 10k 50k v cc = 9v 80a 50k 100k 5 7 fnc_vcr fnc_aux function switching input (scart pin 8). typical levels = 0v/6v/12v 5 7
?9 CXA2078Q electrical characteristics absolute maximum ratings supply voltage vcc_12v 12 v operating conditions supply voltage vcc_12v 12 to 10.7 v voltage regulation vreg_9v 9 0.45 v (from 12v supply) operating voltage video_vcc, dig_vcc, 9 0.5 v audio_vcc 9 0.5 v fnc_tva (pin 38) and fnc_tvb (pin 39) are static sensitive. precaution should be taken (note 8 in "notes on operation"). operation of the CXA2078Q using a 9v supply connected directly to the v cc _12v, video_v cc , audio_v cc and dig_v cc pins is possible but not recommended. (the unused on-chip voltage regulator is then forced to have pins vreg_base and vreg_9v floating.)
?10 CXA2078Q electrical characteristics nominal conditions (ta = 25?) v cc _12v = 12v, no signal, no load current consumption i cc 30 50 70 ma item symbol conditions min. typ. max. unit video system nominal conditions (ta = 25?, vcc_12v = 12v) input pin voltage output pin voltage gain (except y/c mixer) gain of y/c mixer bandwidth (except y/c mixer) bandwidth of y/c mixer input dynamic range output dynamic range cross talk s/n ratio input impedance non-linearity differential gain differential phase sync crush delay of luma over chroma through mixer v vpin v vpout v vpoutm gvv gv yc f v3db f yc3db v drvi v drvo vctv s/n v zin v lin dg dp sc tcld 4.3 3.6 3.5 5.5 5.4 15 7 2.5 5.0 94 ? 4.6 3.9 3.8 6.0 6.0 20 15 72 120 ?.4 1.5 1 0.2 15 4.9 4.2 4.2 6.5 6.4 ?0 +3 3 40 v v v db db mhz mhz vp-p vp-p db db k % % deg % ns item symbol conditions min. typ. max. unit vout1 ?8 vout8 (mix) v1 v2 input/v v2 v1 2 no signal, no load (fig.1) no signal,no load,y/c mix inactive (fig.1) no signal, no load, y/c mix active (fig.1) f = 200khz, 0.3vp-p input (fig.2) f = 200khz, 0.3vp-p input (fig.2) 0.3vp-p input, frequency where output level is ?db with 200khz serving as 0db (fig. 2) 0.3vp-p input, frequency where output level is ?db with 200khz serving as 0db. no trap connected. (see note below) (fig.2) 200khz input (fig.2) 200khz, 2.5vp-p input (fig.2) f = 4.43mhz, 1vp-p input (fig.2) ratio of 0.7vp-p white video signal to black line noise. weighted using ccir 567. hpf @ 5khz, lpf @ 5mhz. (fig.2) 1vrms 1khz input through 56k . attenuation measured to calculate zin v (fig.3) (fig.4) v1 = pin voltage +0.5v v2 = pin voltage +1v at output, non-linearity = ? 100 1.7vp-p 5-step modulated staircase. (chroma and burst are 150mvp-p 4.43mhz) (fig.2) as above. (fig.2) percentage reduction in sync pulse (0.4vp-p), with tip at ?.2v input offset. (fig.4) 0.4vp-p square wave input. input to output edge delay measured. no trap. (fig.2) note) input output path from vin9 ?12 to vout 8 through mixer has bw reduced by external stray capacitance on trap pin.
?11 CXA2078Q electrical characteristics audio system unless otherwise stated: input coupling capacitor 1? in series with 6k resistor; output coupling capacitor of 10?; load of 10k . nominal conditions (ta = 25?, vcc_12v = 12v) no signal, no load (fig. 5) f = 1khz, 1vrms input. (fig. 6) f = 1khz, 1vrms input. (fig. 6) f = 1khz, 1vrms "stereo" input. (fig. 6) 0.3vp-p input. output level at 30khz with 1khz serving as 0db. 6k removed. (fig. 7) 0.3vp-p input; frequency where output level is ?db with 1khz serving as 0db. 6k removed. no load (fig. 7) f = 1khz, 0.5vrms, unweighted response; lpf @400hz, hpf @ 80khz. (fig. 6) f = 1khz (fig. 6) f = 1khz, 1vrms input on one input, measure on any other audio output. (fig.6) f = 100hz, 0.3vp-p applied to vcc_aud (fig. 8) f = 100hz, 0.3vp-p applied to vcc_aud (fig. 8) f = 100hz, 0.3vp-p applied to vcc_aud (fig. 8) offset voltage between any audio input and r/lout1, 2 (fig. 5) (excluding series external 6k ) (excluding any external series resistor) f = 1khz, 1vrms input to two channels. phase difference of stereo output measured f = 1khz, 1vrms input (at maximum volume). hpf @ 20hz, lpf @ 20khz. (fig. 6) f = 1khz, 0.5vrms input. set by i 2 c (fig.6) f = 1khz, 0.5vrms input. set by i 2 c (fig.6) f = 1khz, 1vrms input. (fig.6) offset voltage between any audio input and rtv, ltv outputs (fig.5) input pin voltage gain audio frequency response frequency b/w distortion input dynamic range cross talk (channel separation) ripple rejection dc offset -r/lout1, 2 input impedance output impedance phase difference s/n ratio electronic volume control fine volume attenuation step coarse volume attenuation step mute dc offset -rtv, ltv v apin gv a gv atv gv am f af f bwa1 thd v da v cta rr a rr atv rr am voff zin zout vpda s/n a a evc a evf amute vofftv 4.2 ?.5 ?.65 ?.65 ?.3 2 ?0 48 72 0.6 7.5 ?0 4.5 0 0 0 0 1 0.004 ?8 ?2 ?5 ?4 +2 60 10 0.05 95 1 8 >80 +2 4.8 +0.5 +0.35 +0.45 +0.3 0.2 ?6 +30 72 1.4 8.5 +30 v db db db db mhz % vrms db db db db mv k deg db db db db mv item symbol conditions min. typ. max. unit r/lout1, 2 rtv, ltv mono r/lout1, 2 rtv, ltv mono
?12 CXA2078Q +12v 1k 1k 25pf 47h trap switch sw1 +12v +9v bc547b bc547b 1k +12v bc547b 1k +12v bc547b 1k +12v bc547b 1k +12v bc547b 1k 22f +12v bc547b 1k +12v bc547b 1k +9v bc547b +12v +9v +9v measurement point measurement point scl sda 47f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 fig. 1. video system (d.c.test) notes) 1. all +9v supplies de-coupled close to supply pins, 25, 47, 58 with 10nf ceramic capacitor. 2. all video outputs are loaded with emitter follower during tests. 3. voltage measurements carried out with a high input impedance dvm. typically 10g .
?13 CXA2078Q +12v 1k 1k 25pf 47h trap switch sw1 +12v +9v bc547b bc547b 1k +12v bc547b 1k +12v bc547b 1k +12v bc547b 1k +12v bc547b 1k 22f +12v bc547b 1k +12v bc547b 1k +9v bc547b +12v +9v +9v input signal measurement point scl sda 47f 2.2f 75 75 2.2f 75 2.2f 75 2.2f 75 2.2f 75 2.2f 75 2.2f 75 2.2f 75 2.2f 75 2.2f 75 75 2.2f 2.2f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 fig. 2. video system (gain, dynamic range, bandwidth, differential gain, differential phase, crosstalk, signal to noise, luma-chroma delay) signal applied to pins 2, 4, 6, 8, 14, 16, 18, 20, 22, 24, 62, 64 output signal measured from pins 27, 29, 31, 33, 48, 50, 52, 54 notes) 1. all +9v supplies de-coupled close to supply pins, 25, 47, 58 with 10nf ceramic capacitor. 2. for tests requiring video measuring equipment with 75 input impedance, an external video line driver or buffer is used. 3. for bandwidth tests through y/c mixer, the trap circuit is switched out using sw1. 4. all video outputs are loaded with emitter follower during tests. 5. for luma and chroma input to output delay, measure signal at the i.c. pins.
?14 CXA2078Q +9v 22f +9v bc547b +12v +9v +9v signal input scl sda 47f 56k 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 56k 2.2f 2.2f 56k 56k 56k 56k 56k 2.2f 2.2f 2.2f 56k 56k 56k 56k 2.2f 56k measurement point 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 fig. 3. video system (input impedance) signal applied and measured from pins, 2, 4, 6, 8, 14, 16, 18, 20, 22, 24, 62, 64 notes) 1. all +9v supplies de-coupled close to supply pins, 25, 47, 58 with 10nf ceramic capacitor. 2. voltage measurements carried out with a high input impedance dvm. typically 10g .
?15 CXA2078Q +12v 1k 1k 25pf 47h trap switch sw1 +12v +9v bc547b bc547b 1k +12v bc547b 1k +12v bc547b 1k +12v bc547b 1k +12v bc547b 1k 22f +12v bc547b 1k +12v bc547b 1k +9v bc547b +12v +9v +9v input signal measurement point scl sda 47f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 psu fig. 4. video system (linearity, sync crush) signal applied to pins, 2, 4, 6, 8, 14, 16, 18, 20, 22, 24, 62, 64 output signal measured from pins 27, 29, 31, 33, 48, 50, 52, 54 notes) 1. all +9v supplies de-coupled close to supply pins, 25, 47, 58 with 10nf ceramic capacitor. 2. all video outputs are loaded with emitter follower during tests.
?16 CXA2078Q +9v 22f +9v bc547b +12v +9v +9v input measurement point output measurement point scl sda 47f +9v hw mute sw1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 fig. 5. audio system (d.c. tests) notes) 1. all +9v supplies de-coupled close to supply pins, 25, 47, 58 with 10nf ceramic capacitor. 2. voltage measurements carried out with a high input impedance dvm. typically 10g .
?17 CXA2078Q hw mute +9v bc547b +12v +9v +9v input signal measurement point scl sda 47f 1f 600 600 1f 22f 6k 600 6k 600 6k 600 6k 1f 1f 1f 6k 10k 10f 10k 10f 10k 10f 10k 10f 10k 10f 600 1f 6k 600 1f 6k +9v sw1 10k 10f 10k 10f 600 1f 6k 600 1f 6k 600 1f 6k +9v 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 notes) 1. all +9v supplies de-coupled close to supply pins, 25, 47, 58 with 10nf ceramic capacitor. 2. when muting audio using hardware mute, sw1 is closed. fig. 6. audio system (gain, dynamic range, signal to noise, crosstalk, distortion, volume control) signal applied to pins, 63, 1, 59, 61, 15, 17, 19, 21, 36, 39 output signal measured from pins 26, 28, 30, 32, 34, 49, 51
?18 CXA2078Q hw mute +9v bc547b +12v +9v +9v input signal measurement point scl sda 47f 1f 600 600 1f 22f 600 600 600 1f 1f 1f 10k 10f 10k 10f 10k 10f 10k 10f 10k 10f 600 1f 600 1f +9v sw1 10k 10f 10k 10f 600 1f 600 1f 600 1f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 +9v note) all +9v supplies de-coupled close to supply pins, 25, 47, 58 with 10nf ceramic capacitor. fig. 7. audio system (bandwidth) signal applied to pins, 63, 1, 59, 61, 15, 17, 19, 21, 36, 39 output signal measured from pins 26, 28, 30, 32, 34, 49, 51
?19 CXA2078Q hw mute +9v bc547b +12v +9v measurement point scl sda 47f 1f 600 600 1f 22f 6k 600 6k 600 6k 600 6k 1f 1f 1f 6k 10k 10f 10k 10f 10k 10f 10k 10f 10k 10f 600 1f 6k 600 1f 6k +9v sw1 10k 10f 10k 10f 600 1f 6k 600 1f 6k 600 1f 6k +9v 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 +9v 100hz 0.3vp-p note) all +9v supplies de-coupled close to supply pins, 25, 47, 58 with 10nf ceramic capacitor. fig. 8. audio system (ripple rejection) output signal measured from pins 26, 28, 30, 32, 34, 49, 51
?20 CXA2078Q 600 10 vout2 fblk_out vout1 v cc _12v vreg_9v vreg_base video_v cc rin5 fblk_in2 lin5 vin1 rin1 vin3 rout1 vout5 lout1 vout6 rout2 vout7 lout2 audio_v cc vin12 bias_audio vin8 lin3 vin4 rtv vout3 ltv vout4 dig_v cc log_1 log_2 log_3 log_4 dig_gnd fblk_in1 hw mute lin4 fnc_tva fnc_tvb rin4 trap mono vout8 lin1 vin5 bias_video vin9 fnc_vcr vin6 fnc_aux vin10 video_gnd scl sda adr audio_gnd vin7 rin2 vin11 lin2 vin2 rin3 10k 10k 2.2k 2.2k bc547b 50 1k 6k 1 audio4_l hw_mute 75 10k 10k 10k 10k 1k +12v 9v_reg 4.7 10nf 600 10 75 75 75 75 6k 1 audio4_r 47h 27pf 1k to modulator +12v bc547b bc547b 600 10 75 +12v 75 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 21 600 10 600 10 bc547b bc547b +12v bc547b 1k vcr scart 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 21 aux scart 600 10 4.7 10nf 9v_reg 75 1 6k 75 0.47 75 75 75 75 10k 0.47 22 0.47 6k 1 0.47 1 6k 0.47 1 6k 0.47 10k i 2 c 0.47 0.47 0.47 0.47 1 6k 47 0.47 1 6k 0.47 encoder 4.7 l 6k 6k 1 1 10nf +12v 47 r audio 5 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 21 t. v. scart 5 1k 75 20 21 22 23 24 25 26 27 28 29 30 31 32 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 CXA2078Q bc547b bc547b bc547b 1k 1k bc547b typical application circuit
?21 CXA2078Q description of operation 1. explanation of video section the video section comprises of 12 high impedance (120k ) inputs switched through to 8 video outputs. a +6db internal amplifier is connected to each output. the amplifier is required to compensate for the 6db attenuation which occurs at the external emitter follower stage used for driving video loads. the typical external configuration is shown in fig. 1-1. a y/c mixer can be used for mixing luma and chroma signals for use with an external rf modulator connected to vout8. the y/c mixer is controllable via the i 2 c data bus. the circuit is shown in fig. 1-2 with a trap circuit used to give 3db attenuation at 4.43mhz of the luma signal. amp scart_in 75 w 75 w 0.47 vin 120k w vbias video element switch vbias video_v cc = 9v vout bc547b 1k w 75 w beta = 250 scart_out 75 w load v cc = 12v 1k w 6db 6db 1k w 0db 0db 6db 6.5k w 6.5k w 147 w 1k w 47f 25pf trap vout8 vout4 vout3 r/c cvbs/y fig. 1-1. video circuit element: 6db gain amplifier with external emitter follower fig. 1-2. y/c mixer circuit
?22 CXA2078Q 2. explanation of audio system. audio switch and amplifier the audio system consists of 5 stereo inputs, 3 stereo outputs and a mono output. each output can be independently connected to any one of five inputs, lin1 to lin5 for the left stereo audio channel, and rin1 to rin5 for the right hand audio channel. in all cases, the input to the switch and amplifier is composed of a potential divider consisting of a 27k series resistor and a 33k connected to a voltage source (4.5v). when used in conjunction with an external 6k series input resistor, the input configuration forms a ?db attenuator (fig. 2-1). the net gain of the audio system is zero as there is an internal +6db amplifier on each output. the output impedance of the audio amplifier is near zero, and is used to drive the external scart circuit. the output is capacitively coupled through a 10? capacitor, and an optional 600 series compliance resistor. depending on the length and type of cable used in the scart cable connector, the load seen at the scart terminal will consist of a parallel capacitor, (100pf to 400pf) and mandatory 10k resistor connected to ground (fig. 2-2). the customer may chose to place an alternative audio output filter at the av switch output. tv audio output the tv audio section is composed of an audio switch and 0db amplifier followed by two variable gain stages, corresponding to the course and fine electronic volume control amplifiers, evc and evf. the evc amplifier attenuates the input signal in steps of 8db. a range of attenuation from 0db to 56db can be programmed by means of the i 2 c interface. similarly, the fine volume control (evf) can be programmed to provide a range of attenuations between 0db and 7db. the attenuated signal is passed through to the output buffer stage which provides the necessary +6db gain, and is used to drive the scart connector. the final output buffer can also act as a ?0db (mute) amplifier (fig. 2-4). zero cross detector (zcd) the zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio mute. the change volume or mute instruction sent by i 2 c will only be implemented when a minimal (ie zero cross) signal amplitude is detected. the zero cross detection circuit can be turned off by setting the "zcd" bit low in the i 2 c write mode. the status of the zero cross detector can be checked in the i 2 c read mode (z.c status). when this bit is high, a zero cross condition has been detected subsequent to the issue of an i 2 c volume change or mute instruction. this may be useful if the input waveform is very low frequency, whereupon the microprocessor can re-issue the same instruction, with the zero cross detector circuit switched off. i 2 c mute the mute instruction in the i 2 c format refers to the tv audio circuit. audio mute can be implemented after a audio zero cross detection, or immediately depending on whether zcd = 1 or 0. it can be seen from the i 2 c write format that the same mute bit occurs in data1 and data5. this allows the software to action an immediate mute, make any suitable changes to the audio source or electronic volume control and after a minimum period of 4 90? (360?) un-mute the output buffer. such a period provides ample time to allow any transient ac voltages to settle during an audio source change.
?23 CXA2078Q 33k w 600 w 4.5v 27k w 6k w 1f r/l in att = ?db (internal) (external) audio in terminal 10k w 600 10f scart (external) audio out 400pf audio output 4.5v ?db att att att att att +6db mute r/l in r/l in r/l in r/l in r/l in audio switch att att att att att mute mute (?0db) tv audio output zero cross detect to control logic 0 to ?6db 0 to ?db 0db i 2 c registers evc evf +6db fig. 2-1. audio input configuration fig. 2-2. audio output configuration fig. 2-3. vcr and aux audio configuration fig. 2-4. t.v. audio section and electronic volume control
?24 CXA2078Q i 2 c interface data format ic control data format slave address a data1 a data2 a data3 a data4 a data5 a p s s: start condition a: acknowledge p: stop condition there are two possible addresses depending on external address pin (12) tied high or low. pin 12 = high, address = 92 hex ao = 1 pin 12 = low, address = 90 hex ao = 0 general i 2 c data structure (write mode) address data1 data2 data3 data4 data5 b7 1 evc vid_sw1 (tv) vid_sw2 (vcr) vid_sw3 (aux) x log4 x f blk fnc x x y/c mix tvmute b6 0 b5 0 b4 1 evf b3 0 b2 0 b1 ao b0 (w) 0 tvmute z.c.d aud_sw1 (tv) aud_sw2 (vcr) aud_sw3 (aux) log2 log3 log1 key evc: electronic volume course (8db steps) evf: electronic volume fine (1db steps) tvmute: tv audio mute. controls the tv audio output buffer. (same bit appears in data 1 & 5) z.c.d: zero cross detector active. when zcd = 1 volume and mute change at zero cross. vid_sw1: selects the input video sources for vout1, vout2, vout3, vout4 vid_sw2: selects the input video sources for vout5, vout6 vid_sw3: selects the input video sources for vout7 aud_sw1: selects one of 5 stereo inputs for rtv, ltv aud_sw2: selects one of 5 stereo inputs for rout1, lout1 aud_sw3: selects one of 5 stereo inputs for rout2, lout2 fnc: video function switch control fblk: video fast blanking control y/c mix: when y/c mix = 1 converts y/c input to cvbs for output through vout8 log1-log4: logic outputs (open collector). 0 = high impedance. 1 = current sink mode.
?25 CXA2078Q general i 2 c data structure (read mode) slave address a data6 p na s na: no acknowledge data structure slave address data6 b7 1 x b6 0 x b5 0 zc status b4 1 p.o.d. func_aux b3 0 b2 0 b1 x b0 (r) 1 func_vcr func_vcr: at pin 5 av switch monitors the voltage of pin 8 from vcr scart, and records status. func_aux: at pin 7 av switch monitors the voltage of pin 8 from aux scart, and records status. zc status: zc status = 1 indicates that zero cross condition has been achieved after a volume or mute instruction issued. p.o.d.: power on detect. p.o.d. = 1 when dig_v cc voltage rises above a threshold level of approximately 5v.
?26 CXA2078Q 3. video input i 2 c control 3-1. video switch 1 (vid_sw1) ?tv output vout1 vout2 vout3 vout4 comment 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 vin1 vbias vbias vin2 vbias vin1 vin1 vbias vin3 vbias vbias vin4 vbias vin3 vin3 vbias vin5 vin6 vin7 vin8 vin5 vin5 vin5 vbias vin9 vin10 vin11 vin12 vin3 vin10 vin11 vbias digital encoder digital encoder vcr aux digital encoder digital encoder digital encoder video mute b g/cvbs/y r/c cvbs/y d2_b5 d2_b4 d2_b3 vout5 vout6 comment 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 vin5 vin6 vin7 vin8 vin5 vbias vbias vbias vin9 vin10 vin11 vin12 vin3 vbias vbias vbias digital encoder digital encoder vcr aux digital encoder video mute video mute video mute chroma (c) cvbs/y d3_b5 d3_b4 d3_b3 table 3-1. showing which video input pins connect to the four tv output pins 3-2. video switch 2 (vid_sw2) ?vcr output table 3-2. showing which video input pins connect to the two vcr output pins
?27 CXA2078Q 3-3. video switch 3 (vid_sw3) ?aux output vout7 comment 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 vin9 vbias vin11 vin12 vin3 vbias vbias vbias digital encoder video mute vcr aux digital encoder video mute video mute video mute cvbs d4_b5 d4_b4 d4_b3 table 3-3. showing which video input pins connect to the single aux output pin
?28 CXA2078Q 4. fast blanking operation (pin 16 on scart), fblk the fast blanking signal instructs the tv to select either the external cvbs information or the external rgb information. this is used to impose an on screen display (osd) presentation (normally rgb) upon a cvbs background. fast blanking information has the same nominal phase as the rgb and cvbs signal, and is defined as follows, fast blanking output at scart, 1. cvbs mode scart pin voltage = 0 to 0.4v 2. rgb mode scart pin voltage = 1 to 3.0v threshold voltage is approximately 0.75v dc voltage at scart input. the blanking information is usually generated by the same source as that producing the rgb signal. i 2 c control in the CXA2078Q, there are two fast blanking inputs, one associated with the auxiliary rgb/cvbs inputs and another associated with digital encoder input. these can be selected by i 2 c. in addition to the two blanking inputs, the fast blank pin output can be set to a constant 0v or 5v by means of the i 2 c control. hence there are four possible states. these are controlled according to the following table. fblk_out (pin 53) 0v * 1 5v same state as fblk_in1 (0/5v) same state as fblk_in2 (0/5v) d2_b7 0 0 1 1 d2_b6 0 1 0 1 fblk * 1 default = 0v at power up
?29 CXA2078Q slave address b7 1 b6 0 b5 0 b4 1 b3 0 b2 0 b1 x b0 (r) 1 data6 z.c status p.o.d. func_aux func_vcr 5. function switch, fnc. the function switch facility is designed to read the status of the scart function pin 8 from the vcr and aux inputs (ic pin 5, 7). the output function pins fnc_tva and fnc_tvb are controlled from the ic using a write instruction. a suitable interface circuit (fig 5-2) will allow fnc_tva and fnc_tvb to instruct the tv to switch between display modes. read mode data structure read mode status of i 2 c registers as a function of the voltage on fnc_aux (pin 7) and fnc_vcr (pin 5) 0 0 1 b3/b1 0 0 1 1 d3_b7 0 1 0 1 d3_b6 2v 0v 0v 0v fnc_tva pin voltage 2v 2v 0v 0v fnc_tvb pin voltage internal tv (default) external 16:9 external 4:3 external 4:3 comment 0 1 1 b2/b0 0v to +2v (default) +4.5 to +7v +9.5 to +12v fnc_aux or fnc_vcr (internal tv) (16:9 external) (4:3 external) level (scart defn) read data6 input pin voltage write mode tv function switch, interface table default is internal tv (0, 0) at power up
?30 CXA2078Q the two function output pins are controlled via logic to swing from 0 to +2v. logic drive circuit mux d3_b7 d3_b6 fnc_tva (38) fnc_tvb (37) < 0.4v < 0.4v 2v 2v fig. 5-1. tv function switch output some external circuitry is required to interface from the ic pins to the scart pin 8. a typical interface circuit is shown in fig. 5-2. 50 w 2.2k w 1k w 2.2k w 1k w 12v tv scart pin 8 fnc_tva fnc_tvb CXA2078Q fig. 5-2. external circuit for function switch
?31 CXA2078Q 6. logic outputs i 2 c control of logic outputs achieved using bits log1 ?4. specification i 2 c bit 0 = open collector/high output impedance on logic pin i 2 c bit 1 = current sink mode resulting in 0.2v saturation voltage on logic pin vmax at logic pin = 12v imax during current sink = 1ma 10k w log_1 10k w log_2 10k w log_3 10k w log_4 logic cct. d5_b3 d5_b2 d5_b1 d5_b0 logic cct. external resistors v cc = 9v fig. 6-1. open collector logic outputs
?32 CXA2078Q 7. i 2 c audio signal control i 2 c audio input select using aud_sw1 (tv), aud_sw2 (vcr), aud_sw3 (aux) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 b2 b1 b0 rin1 rin2 rin3 rin4 rin5 audio mute audio mute audio mute lin1 lin2 lin3 lin4 lin5 audio mute audio mute audio mute rtv, rout1, rout2 ltv, lout1, lout2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 b7 b6 b5 0 ? ?6 ?4 ?2 ?0 ?8 ?6 gain (db) i 2 c electronic volume control (coarse) data 1, evc 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 b4 b3 b2 0 ? ? ? ? ? ? ? gain (db) i 2 c electronic volume control (fine) data 1, evf
?33 CXA2078Q 0 0 1 1 0 1 0 1 tv mute data1 b1 data5 b7 z.c.d data1 b0 un-mute immediately un-mute on next zero cross mute immediately mute on the next zero cross rtv, ltv, mono output i 2 c mute function notes on operation 1) supply de-coupling capacitors, 10nf and 4.7? in parallel should be inserted as close to the supply pins, 25, 47, 58 as possible. 2) to minimise crosstalk, attention should be given to the routing of audio and video to the ic inputs. pcb track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 3) the trap components on pin 35 should be kept as close to the ic as possible to minimise parasitic capacitance to ground. 4) attention should be given to the electrolytic capacitors on the input and output signal pins. as the pin's voltage is between 3.7v and 4.7v dc the positive terminal on the capacitor should be orientated towards the pin. 5) the audio outputs may be muted at any time after power up by connecting the hw mute pin (40) to a voltage > 2.5v and < 9v. 6) the i 2 c address of the ic can be changed using the adr pin (12). by connecting this pin to >5v and <9v the address changes from 90h to 92h. 7) when driving video loads with impedance = 75 an emitter follower or video line driver is required to be connected at the video outputs. stray capacitance on pins vout1-8 must be kept to a minimum by placing loads as close to the pins as possible. 8) as shown on the application schematic, static protection for pins 38 and 37 may typically be achieved using zener diodes. diodes with a zener voltage > 5v are suitable.
?34 CXA2078Q 0 1 2 3 3.66 0.001 0.01 0.1 1 typical audio output distortion input [vrms] thd [%] input = 1khz, 400hz ?80khz bpf video frequency characteristics video input/output gain [db] 100k frequency [hz] 1m 10m 50m 0 2 4 6 8 v out 1-8 (mix = off) v out 8 (mix = on) input = 0.3vp-p audio frequency characteristics audio input/output gain [db] 100 1k 10k 100k 1m ? ? ? 0 2 4 frequency [hz] note: audio input 6k w resistor removed for this test. input = 0.3vp-p
?35 CXA2078Q package outline unit: mm sony code eiaj code jedec code 23.9??.4 20.0?.1 0.4 ?0.1 + 0.15 14.00.1 1 19 20 32 33 51 52 64 0.15 ?0.05 + 0.1 2.75 ?0.15 16.3 0.1 ?0.05 + 0.2 0.8 0.2 m 0.12 0.15 +?.4 17.9??.4 +0.4 + 0.35 64pin qfp(plastic) qfp?4p?01 qfp064??420 package material lead treatment lead material package mass epoxy resin solder/palladium 42/copper alloy package structure plating 1.5g 1.0

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